1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device, and a semiconductor device manufactured by the method.
2. Related Art
An example of a conventional vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is disclosed in Japanese Unexamined Patent Application Publication No. 2005-505912.
This MOSFET is designed to reduce the gate-drain parasitic capacitance and improve the switching characteristics by providing a source-potential-applied polysilicon shield layer below a polysilicon gate electrode in a power transistor having a trench gate electrode.
FIGS. 14 and 15 illustrate the device disclosed in Japanese Unexamined Patent Application Publication No. 2005-505912. FIG. 15 is a cross-sectional view taken along the line E-E′ of FIG. 14. In this semiconductor device, an epitaxial layer 1014 to be a low-doped drain region is formed on a substrate 1008 to be a high-doped drain region. The trench gate structure of this semiconductor device includes a gate insulating film 1032, a polysilicon gate electrode 1034, and an interlayer insulating layer 1033 formed over the gate insulating film 1032 and the polysilicon gate electrode 1034. The trench gate structure further includes a polysilicon shield layer 1038 embedded below the polysilicon gate electrode 1034 via an insulating layer 1036. A base region 1016 and a source region 1018 are formed on either side of the trench gate structure, with the source region 1018 being located above the base region 1016. The source region 1018 is connected to a source electrode 1020 formed above the source region 1018. The polysilicon shield layer 1038 extends to the outer peripheral portion of the die, and is electrically connected to the source electrode 1020, as shown in FIG. 15. In other words, the polysilicon shield layer 1038 having the same electrostatic potential as the source electrode 1020 is interposed between the polysilicon gate electrode 1034 and the drain region (the epitaxial layer 1014). With this arrangement, the switching loss caused when the gate-drain parasitic capacitance is charged and discharged during a switching transition is reduced by the polysilicon shield layer 1038 fixed at the source potential. Accordingly, the switching characteristics are improved.
However, the present inventor has recognized the following problems. According to Japanese Unexamined Patent Application Publication No. 2005-505912, the polysilicon gate electrode 1034 and the polysilicon shield layer 1038 need to be connected to the gate electrode 1039 and the source electrode 1020, respectively, as shown in FIG. 15. Therefore, the procedure for patterning the polysilicon gate electrode 1034 and the procedure for patterning the polysilicon shield layer 1038 are required. Furthermore, since the polysilicon shield layer 1038 and the source electrode 1020 are connected at the outer peripheral portion of the die, a large area is required, and the size of the die becomes large. To counter those problems, the inventor decided to make further improvements.